1. Technical Field
The present invention relates to a method to manufacture high aspect ratio traces, tools used in the method and electronic circuit structures created with such traces.
2. Related Background Art
Manufacturers of popular portable electronic equipment such as cell phones and personal computers have placed enormous stresses on the interconnect industry. Hybrid circuit and printed circuit board (PCB) customers continue to demand smaller form factors, higher performance and more features. The two primary forces driving these requirements are the continued increase of semiconductor density and cost. Consequently, there is pressure on the interconnect industry to provide: 1) finer geometries (10 μm and below), 2) better line width control, 3) thinner dielectrics, and 4) better electrical performance. Process costs need to be lower than current high-density solutions. Additionally, entry barriers for the production processes necessary to achieve these requirements should be low and allow smaller manufacturers to produce high-quality and high-density substrates, preferably using existing equipment and manufacturing processes.
Imprint patterning presents an elegant solution to the contradictory requirements of high performance and low entry barriers. Imprint patterning replaces alternative and more expensive photolithography and laser drilling processes with a simple and cost-effective microreplication step. It produces features for all circuit traces and interconnect vias for a particular layer simultaneously. It avoids the masking and registration steps in conventional PCB manufacturing processes that contribute to density constraints and scrap. Importantly, it can be implemented in virtually any printed circuit shop with minimal additional equipment and process development expense. The basic tools and methods for imprint patterning of PCBs are described in U.S. Pat. Nos. 5,334,279; 5,390,412; 5,451,722; 6,005,198; 6,460,247 and RE38,579; all by the inventor and all hereby incorporated by reference.
Although imprint patterning produces interconnect circuits at lower cost and with higher circuit density, it has heretofore resulted in a typical multilayer structure having low aspect ratio traces (wider than they are tall) that produce large parasitic capacitances between traces on different layers or between traces and ground or power planes. These parasitic capacitances limit electronic performance of the assembled circuitry in that they provide unintended spurious signal coupling paths between isolated traces that can cause excessive system noise or cause excessive capacitive loading of sensitive circuits that can slow down operating waveforms.
Prior attempts to reduce these performance limiting parasitic capacitances have involved reducing trace dimensions while increasing interlevel dielectric thicknesses. Unfortunately, as experienced similarly in the semiconductor industry, these measures result in adding expensive, special purpose processes that add significantly to the cost of the product, while simultaneously erecting significant entry barriers in the form of new equipment capitalization costs.
Therefore, it is desirable to provide a new and improved imprint patterning process for PCBs and other interconnect circuits that includes the ability to fabricate high aspect ratio traces (taller than they are wide) having particularly narrow widths compared to and in addition to conventional imprinted traces.